The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for fabricating a semiconductor device capable of improving a gap-fill property of a conductive wire.
As a cell size of a semiconductor memory device has been extensively micronized, a capacitor height needs to be increased in order to secure a high capacitance, and this trend further results in an increase of a thickness of an insulation layer.
To meet a demand of large-scale integration, a specific range of an etch thickness of the insulation layer for insulating each unit device is required to make a contact with another insulation layer at bottom. For instance, the etch thickness of the insulation layer for making a connection with a power line of a bit line ranges from about about 15000 xc3x85 to about 20000xc3x85.
An implementation of a hard mask partially solves a problem of an excessive etch of an etch target for forming a deep contact hole. However, the more severe problem arose from the above etch process for forming the deep contact hole is a bowing profile wherein an etched surface slightly gets bent.
In the etch process for forming the deep contact hole, the above bowing phenomenon takes place at a thickness of the etch target, e.g., the insulation layer, typically ranging from about 2000 xc3x85 to about 10000xc3x85.
The factor causing the bowing phenomenon is radicals or ion bombardments that make the insulation layer etched excessively at the thickness in a range from about 2000 xc3x85 to about 10000 xc3x85. The incident ions and radicals are reflected at the aforementioned thickness and causes bottom parts to be etched, and thereby pronouncing the bowing phenomenon at the bottom portions.
Also, the bowing phenomenon gives rise to a void generation in the course of burying a conductive wire or plug material into a contact hole, and the void generation may further induce a seam generation.
FIG. 1 is a cross-sectional view showing a peripheral circuit region completed with a metal wire formation of a conventional semiconductor memory device.
As shown, a conductive layer 11 and an insulation layer 12 for a hard mask (hereinafter referred to as a hard mask insulation layer) are sequentially stacked to form a bit line pattern on a substrate 10. At lateral sides of the bit line pattern, an insulation layer 13 for a spacer (hereinafter referred to as a spacer insulation layer) is formed.
Herein, the conductive layer 11 is made of poly-silicon or tungsten. The hard mask insulation layer 12 and the spacer insulation layer 13 are nitride-based layers having a higher etch tolerance than that of a silicon oxide layer. Examples of the nitride-based layer are a silicon nitride layer and a silicon oxynitride layer.
On top of the bit line pattern, an insulation layer 14 is formed, and an opening H, i.e., a contact hole, is formed by passing through the insulation layer 14 and the hard mask insulation layer 12. Then, a diffusion barrier layer 16 is formed along lateral walls and a bottom surface of the contact hole H. A conductive wire 15 such as a metal wire or a plug is filled into the contact hole H.
Meanwhile, the insulation layer 14 is formed in the peripheral circuit region while a capacitor is formed in a cell region. Thus, the insulation layer 14 has a thick thickness of above about 10000 xc3x85. Also, the insulation layer 14 has a structure with more than double layers.
As the semiconductor device has been highly integrated, the thickness of the insulation layer 14 is also increasingly augmented in order to improve the capacitance. On the other hand, a width of the bit line pattern gets narrower. As a result of these trends, an aspect ratio of the contact hole H also increases proportionally.
However, a gap-fill property of the conductive wire 15 is degraded because the diffusion barrier layer 16 is previously formed in a region of the contact hole H having a narrow width. Therefore, the void (refer to 17 shown in FIG. 1) is generated within the conductive wire 15. Particularly, the void may be a main cause for degrading an electric property of the semiconductor device.
Furthermore, the conductive wire 15 has a relatively low resistivity but a high resistance because of the degraded gap-fill property.
Accordingly, it is critical to develop a specific method for improving the gap-fill property of the conductive wire formed through the use of the deep contact hole.
It is, therefore, an object of the present invention to provide a method for fabricating a semiconductor device including a conductive wire formed with use of a deep contact hole in order to efficiently improve a gap-fill property of the conductive wire.
In accordance with an aspect of the present invention, there is provided a method for fabricating a semiconductor device divided into a first region and a second region peripheral to the first region, the method including the steps of: forming a plurality of conductive patterns on a substrate in the first region and the second region, wherein each of the conductive patterns includes sequentially stacked layers of a conductive layer and a hard mask; removing the hard mask in the second region to expose the conductive layer; forming a diffusion barrier layer on the exposed conductive layer; depositing an insulation layer on the entire resulting substrate structure in the first region and the second region; selectively etching the insulation layer in the second region to form an opening exposing the diffusion barrier layer; and forming a conductive wire electrically connected to the diffusion barrier layer through the opening.